1. Field of the Invention
This application relates generally to a stack-type semiconductor package, and more particularly to a semiconductor device having one or more semiconductor packages (such as a ball grid array (BGA) package, a thin small outline package (TSOP), and various other packages or chips) stacked therein.
2. Description of the Prior Art
In the art of semiconductor chip packaging, the stack packaging techniques are used to increase the chip density or the memory storage capacity. According to these techniques, two or more semiconductor chips or packages, for example, are stacked on a substrate to form a single semiconductor package, and this type of stack packaging increases the chip density of the resulting packaged semiconductor chip.
One of the known stack packaging techniques is the chip stack package (CSP) technique where the unpackaged chips are stacked and aligned into one semiconductor package. This increases the chip density of the final semiconductor package/chip by about a factor of two.
The other type of known packaging technique is packaging two packaged semiconductor chips into one semiconductor package. For example, two semiconductor packages may be stacked and packaged into a single semiconductor package, and this would also increase the chip density by about a factor two.
FIG. 1 illustrates one type of the CSP-type semiconductor package. As shown, two unpackaged chips 102 and 104 are stacked and aligned on a substrate 106 into a single CSP semiconductor package. The size of each unpackaged chip 102 or 104 is different from the other. On the top surface near the peripheral edges of each chip 102 or 104, active surfaces having a plurality of bonding pads (not shown) are formed. The stacked, unpackaged chips 102 and 104 are then wire-bonded from the bonding pads (not shown) of the chips 102 and 104 to the substrate 106 as the bonding wires are shown in FIG. 1. In this manner, the stacked unpackaged chips 102 and 104 on the substrate 106 are packaged into a single CSP-type semiconductor package.
Another variation of the known CSP technique is shown in FIG. 2. Similar to FIG. 1, two unpackaged chips 204 and 202 are stacked and aligned on a substrate 206 into a single CSP-type stacked semiconductor package. However, instead of using bonding wires, the lower chip 202 is connected to a substrate 206 by using an anisotropic conductive film or a non-conductive film via a set of terminals 208 (such as bumps) formed on the lower chip 202. The upper chip 204 is wire-bonded to the substrate 206 in the similar manner as shown in FIG. 1.
The CSP packaging technique presents several problems and drawbacks. Because the chips that are packaged inside a conventional CSP-type semiconductor package are not packaged, they are subjected to and passed only a probe test, which is not a predictable and reliable measure of determining the package yield rate of the final semiconductor packages. This is because a fault that existed in an unpackaged chip before it is subjected to the CSP technique is almost impossible to detect during the CSP packaging process.
The package yield rate of the CSP technique is typically much less than the yield rate of semiconductor packages/chips produced without utilizing a CSP technique. For example, if the package yield rate of the semiconductor packages/chips produced without utilizing the CSP technique is eighty percent (for example, per one lot of a wafer), the yield rate of the packages/chips produced in a CSP packaging process would typically be about 64%.
The CSP technique is generally intended for producing semiconductor packages in a niche market, because the CSP technique is generally advantageous to a manufacturer who produces the semiconductor packages in small quantities to a particular niche market consumer demand. Nevertheless, this causes the manufacturer to be susceptible to the risks of the fluctuating market demands.
FIG. 3 is a side view showing the conventional technique of packaging two conventional TSOP-type stack packages into a singe package. As shown, two TSOP packages 302 and 304 are stacked to increase the chip density.
This conventional technique also has several limitations. For example, the data bandwidth of a TSOP-type stack package is fixed, and this places limits on the amount of the chip density that can be increased.
In addition, the number of leads in a conventional TSOP-type stack package cannot be increased. So the chips contained in the upper and lower packages 302 and 304 are separately connected to a chip select pin (not shown) and a no-connection pin (not shown). Thus, the final semiconductor package requires an additional no-connection pin.
Further, the two TSOP packages 302 or 304 that are stacked in a final package must be of the same size so that the leads of each package 302 or 304 are arranged in the same position. This conventional packaging technique does not provide ways for packaging two different types of packages into one final semiconductor package or two differences sizes of packages into one final semiconductor package.
Accordingly, there is a need for a method and apparatus for providing a stack-type semiconductor package that contains one or more semiconductor chips and/or packages stacked therein and solves the problems associated with the conventional packaging techniques.